1. Field of the Invention
The present invention relates to a high-speed operation unit, and particularly, to an operation unit applicable to a high-speed microprocessor.
2. Description of the Prior Art
FIG. 1 shows a conventional operation unit that processes 16-bit data at the maximum. The operation unit has a 16-bit operation circuit 103 and temporary registers x101 and y102 directly connected to the data input of the operation circuit 103, to temporarily hold data to be processed. The temporary registers x101 and y102 are connected to 16-bit data buses d1 and d2. The output of the operation circuit 103 is connected to any one of the data buses d1 and d2. For the sake of explanation, the operation unit shown in FIG. 1 has 8-bit registers R1, R2, R3, and R4. The registers R1 and R2 are paired to form a 16-bit register R12, and the registers R3 and R4 are paired to form a 16-bit register R34. The data bus d1 is divided into a lower 8-bit bus d1L and a higher 8-bit bus d1H, and the data bus d2 is divided into a lower 8-bit bus d2L and a higher 8-bit bus d2H. Each of the registers R1 to R4 is connected to all of the 8-bit buses d1L, d2L, d1H, and d2H. During an 8-bit operation, the registers R1 to R4 are connected to the lower 8-bit buses d1L and d2L, and "0" is given to the higher 8-bit buses d1H and d2H when reading the contents of the registers.
A 16-bit operation processed by the operation unit shown in FIG. 1 will be explained with reference to a timing chart shown in FIG. 2. In FIG. 2, "r1" to "r4" are the contents of registers R1 to R4, respectively. And "r12" and "r34" indicate the contents of register pairs R12 and R34, respectively. For example, the contents of the register pair R12, in which the register R1 holds higher 8 bits and the register R2 holds lower 8 bits, are added to the contents of the register pair R34, in which the register R3 holds higher 8 bits and the register R4 holds lower 8 bits, and a result of the operation is written to the register pair R12. Namely, R12+R34.fwdarw.R12. In the first state, the contents of the register pair R12 are transferred to the data bus d1. Namely, the contents of the register R1 are transferred to the higher 8-bit bus d1H, and the contents of the register R2 are transferred to the lower 8-bit bus d1L. At the same time, the contents of the register pair R34 are transferred to the data bus d2. Namely, the contents of the register R3 are transferred to the higher 8-bit bus d2H, and the contents of the register R4 are transferred to the lower 8-bit bus d2L. Thereafter, the contents of the register pair R12 on the data bus d1 are written to the temporary register x101, and the contents of the register pair R34 on the data bus d2 are written to the temporary register y102. In response to an operation control signal f, an addition instruction is given to the operation circuit 103, and "0" is given to a carry input Cin. Then, the operation circuit 103 calculates x+y.
In the second state, the operation circuit 103 provides the data bus d1 with a result of the operation. Namely, the operation circuit 103 provides the higher 8-bit bus d1H with higher 8 bits of the result, and the lower 8-bit bus d1L with lower 8 bits of the result. The result on the data bus d1 is written to the register pair R12. In FIG. 2, "carry" indicates a carry caused by adding the contents of the registers R2 and R4.
An 8-bit operation processed by the operation unit of FIG. 1 will be explained with reference to a timing chart of FIG. 3. For example, the contents of the register R1 are added to the contents of the register R2, and a result of the operation is written to the register R1. Further, the contents of the register R4 are subtracted from the contents of the register R3, and a result of the operation is written to the register R3. Although these operations are 8-bit operations, the operation unit shown in FIG. 1 processes them as 16-bit operations one by one. Namely, the operation of R1+R2.fwdarw.R1 is firstly processed, and then, the operation of R3-R4.fwdarw.R3 is processed. In the first state, the contents of the registers R1 and R2 are transferred to the data buses d1L and d2L, respectively. At this time, the data buses d1H and d2H receive "0." The data on the data buses are transferred to the temporary registers x101 and y102, respectively. In response to the operation control signal f, an addition instruction is given to the operation circuit 103, and "0" is given to the carry input Cin. Then, the operation circuit 103 calculates x+y. In the second state, the operation circuit 103 provides the data bus d1L with a result of the calculation, which is stored in the register R1. In the third state, the contents of the registers R3 and R4 are transferred to the data buses d1L and d2L, respectively, and "0" is given to the data buses d1H and d2H. The data on the data buses d1 and d2 are written to the temporary registers x101 and y102. In response to the operation control signal f, a subtraction instruction is given to the operation circuit 103, and "0" is given to the carry input Cin. Then, the operation circuit 103 calculates x-y. In the fourth state, the operation circuit 103 provides the data bus d1L with a result of the operation, which is written to the register R3. In this way, the conventional operation unit must handle 8-bit operations as 16-bit operations, to idle the higher 8 bits of the operation circuit 103. Since the conventional operation unit must execute 8-bit operations one by one, it needs four states in the case of the above example.
Another operation of the operation unit shown in FIG. 1 that uses a result of the preceding operation will be explained with reference to a timing chart shown in FIG. 4. For example, the contents of the register R1 are added to the contents of the register R2, and a result of the operation is written in the register R1. Thereafter, the new contents of the register R1 are subtracted from the contents of the register R3, and the difference is written to the register R3. The operation unit shown in FIG. 1 must process these operations as 16-bit operations, so that the contents of the register R3 will not be written to the temporary registers x101 or y102 before the first operation of R1+R2.fwdarw.R1 is completed. Accordingly, the process of R3-R1.fwdarw.R3 is carried out only after the completion of the process R1+R2.fwdarw.R1. In the first state, the contents of the registers R1 and R2 are transferred to the data buses d1L and d2L, respectively, and "0" is given to the data buses d1H and d2H. The data on the data buses d1 and d2 are written to the temporary registers x101 and y102, respectively. In response to the operation control signal f, an addition instruction is given to the operation circuit 103, and "0" is given to the carry input Cin. Then, the operation circuit 103 calculates x+y. In the second state, the operation circuit 103 provides the data bus d1L with a result of the operation, i.e., the sum of the contents of the registers R1 and R2, which is written to the register R1. In the third state, the contents of the registers R3 and R1 are transferred to the data buses d1L and d2L, respectively, and "0" is given to the data buses d1H and d2H. The data on the data buses d1 and d2 are written to the temporary registers x101 and y102, respectively. In response to the operation control signal f, a subtraction instruction is given to the operation circuit 103, and "0" is given to the carry input Cin. Then, the operation circuit 103 calculates x-y. In the fourth state, the operation circuit 103 provides the data bus d1L with a result of the operation, i.e., a difference between the contents of the registers R3 and R1, which is written to the register R3.
In this way, the conventional operation unit processes 8-bit operations one by one although it is a 16-bit operation unit, and requires four states in the case of the above example. Namely, it processes an 8-bit binary operation only after the completion of the preceding 8-bit binary operation. Since the conventional operation unit is incapable of simultaneously processing a plurality of operations, it involves a lone processing time.